IEEE

Design and Implementation of 32-bit RISC-V Processor Using Verilog

Abstract: The design and implementation of a 32-bit single-cycle RISC-V processor in Verilog is a sophisticated and elaborate process that aims to create a functioning processor architecture that ...
IEEE

Implementation and Analysis of Mitigation of Distributed Denial of Service Network Time Protocol Amplification Attacks on Software Defined Networks Using Access Control Lists

Abstract: Network Time Protocol amplification attacks can really mess up Software-Defined Networking setups, hammering controllers and throwing IoT networks into chaos. We built a framework that mixes ...